The photolithographic process is one of the most important in semiconductor device fabrication. It transfers the designed pattern from a mask or reticle to photoresist that temporarily coats the wafer surface. The difference between a mask and a reticle is that the former usually has a size corresponding to the entire wafer surface, whereas the latter usually has a size corresponding to only a portion of the wafer surface, known as a field. Whereas a wafer's worth of dies is exposed at one time with a mask, only a wafer field's worth of dies is exposed at one time with a reticle. From a starting position on the semiconductor wafer, a field of the wafer is exposed through the reticle. A stepper then moves, or steps, the reticle to the next field, for exposure of this field through the reticle. This process continues until all the fields of the wafer have been exposed.
FIG. 1 illustratively shows an example of this process. The semiconductor wafer 100 is being exposed through a reticle 102 that has four dies 104a, 104b, 104c, and 104d. Of the four dies 104a, 104b, 104c, and 104d, only the die 104a completely lies on the wafer 100. Once the exposure has occurred, the reticle is stepped to another field on the wafer, either to the left or upward, as indicated by the arrows 106 and 108, respectively. In an organized fashion, the reticle is stepped through the entire wafer 100, so that each field of the wafer 100 is completely exposed through the reticle 102. The left and upwards movement indicated by the arrows 106 and 108, respectively, is for example purposes only, and the movement can just as easily be right and/or downward.
Semiconductor wafers themselves come in a number of different sizes, including five, six, eight, and twelve inches. Smaller wafers are typically easier to handle and manufacture, whereas larger wafers allow for higher device yield, which is the number of devices per wafer. The term semiconductor device is synonymous with die, chip, and so on. The dies fabricated on a semiconductor wafer are separated from one another, and packaged individually, to be sold as integrated circuit (IC) devices.
A common goal of semiconductor designers is to maximize the semiconductor die yield. That is, the semiconductor designers attempt to fit a maximum number of semiconductor devices on a given sized wafer. This number varies depending on a number of factors. For instance, the size of the fields, as well as the size of the dies in each field, affects how many dies can fit on a semiconductor wafer. Also important is the orientation of the fields and their dies on the wafer. Generally, a starting place is selected somewhere on the wafer surface, and the semiconductor wafer is completely covered by fields. The number of whole dies is then counted to determine the maximum number of dies that can fit on the wafer.
FIG. 2 shows illustratively an example of this approach. A starting point 202 is selected on the semiconductor wafer 200. Fields are tiled over the wafer 200 until the surface of the wafer 200 is completely covered. Thus, there are fields over the wafer 200 organized into rows 206a, 206b, and 206c, and columns 204a, 204b, 204c, and 204d. Each field corresponds to a two die-by-two die reticle in this example. The number of the dies of these fields that completely fit within the wafer 200 number sixteen, as counted in FIG. 2 itself. The sixteen fields is grossly small as compared to an actual wafer, and is indicated here as an example only. In reality, hundreds of dies typically fit on a given wafer.
While straightforward in theory, determining the maximum number of dies that can fit on a semiconductor wafer has proven to be difficult in practice. An exhaustive search of all the possible configurations of fields and their dies on a semiconductor wafer is time-prohibitive for minute, precise offsets. That is, examining all possible configurations of fields and their dies from all possible starting points, will likely yield the maximum number of dies in principle, but this approach is time-prohibitive in reality.
Other known approaches sacrifice precision to make the determination more tractable. These approaches may only consider the configuration of fields on a semiconductor wafer, and not the dies of the field, also sacrificing accuracy. They may take a “best guess,” instead of optimizing the configuration for the given reticle, number of dies in the reticle, and the wafer. They typically do not allow for alignment marks, which are marks placed on the surface of a wafer so that the stepper or other semiconductor fabrication equipment can be properly aligned relative to the wafer. Alignment marks take up space on the wafer that otherwise could be used for dies. Even with all these sacrifices, prior art approaches for determining the maximum number of dies that fit on a wafer are still nevertheless slow.
Therefore, there is a need for an approach for determining the maximum number of semiconductor dies that fit on a semiconductor wafer that overcome these problems. Precision and accuracy should not be sacrificed by the approach. Optimization for a given reticle, number of dies in the reticle, and the wafer should be taken into account by the approach. Alignment marks should also be taken into account by the approach. For these and other reasons, there is a need for the present invention.